Method and apparatus for performing register transfer level scan selection

Abstract

A technique for a scan design employing a register transfer level scan selection which requires that either all bits of a register are designated to have all scan or all non-scan properties. No separate elements (bits) of a register are selected for individual scan. By designating scan selection at the register level, register-transfer-level (RTL) specifications of a digital circuit can employ signal flow vectors at the register level and not at the conventional logic gate level. In one technique, a number of registers are grouped to have the same scan or non-scan property. Such grouping is used to provide a common template for inserting scan into multiple instantiated modules. The group designation for selecting scan or non-scan registers is also used to scan registers at the memory input, output, both input and output, or neither, which then can be used for testing memory devices.