The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2001
Filed:
Jul. 02, 1998
Jeffrey R. Brown, Minnetonka, MN (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
A method and computer readable medium are provided for analyzing the integrity of a port list for a component and instantiated modules in a hardware description language file. An example of a hardware description language to which the method and the computer readable medium can be applied is VHDL. The method compares the port lists for a component and associated modules. In the event the component port list and module port list differ, an advisory can be generated to indicated a potential error. The advisory can identify the deviation, and note its location within the hardware description language file. In this manner, the designer can quickly find the port list errors and correct them prior to simulation. Such a port list verification method can significantly reduce the time and effort involved in port list debugging. Consequently, the designer can devote more time and resources to the design effort and the end objective of producing the subject design. In many cases, reduction of debugging costs will bear significantly on the final cost of the design. At the same time, reduction of debugging time can shorten the design cycle.