The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2001
Filed:
Jan. 28, 2000
Cheng-Hsiung Chen, Taipei, TW;
Hsiu-Chin Chen, Taoyuan Hsien, TW;
Shen-Yuan Chou, Hsinchu, TW;
Shih-Yin Hsiao, Chiayi, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
A mixed mode device. A polysilicon layer is over a substrate having a well therein. A first metal layer is formed over the polysilicon layer. A second metal layer is formed over the first metal layer. A conductive type of the well and a conductive type of the substrate are oppositive. A part of the polysilicon layer is positioned over the well. Heavily doped regions are further formed in the well beside the polysilicon layer. The polysilicon layer is used as gates of MOS transistors, and the heavily doped regions are used as source/drain regions of the MOS transistors. The first metal layer over the gate has a finger structure which electrically couples with the drain regions of the MOS transistors. The second metal layer electrically couples with the source regions through vias.