The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 15, 2001

Filed:

Apr. 01, 1998
Applicant:
Inventors:

Brian P. Johnson, Folsom, CA (US);

Dave Freker, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/200 ;
U.S. Cl.
CPC ...
G06F 1/200 ;
Abstract

The present invention discloses a method and apparatus for interfacing a memory array to a memory controller using a field-effect transistor (FET) switch. The memory controller has a bus which comprises a plurality of signal lines. The memory array is coupled to the memory controller. The memory array is divided into N groups of memory devices; each group has K memory devices. K memory devices in each of the N groups share memory signal lines. The FET switch couples the bus to one of the N groups of the shared memory signal lines at different times in response to a switch control indication.


Find Patent Forward Citations

Johnson, Brian. (2001). Using fet switches for large memory arrays (U.S. Patent No. 6233650). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6233650

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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