The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2001
Filed:
Jun. 30, 1999
Wilbur G. Catabay, Saratoga, CA (US);
Wei-Jen Hsia, Sunnyvale, CA (US);
Joe W. Zhao, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
The invention comprises a process for forming a dielectric film having a compressive stress exhibited in the layers deposited onto an integrated circuit structure. This process includes depositing a first thin layer of dielectric material onto an integrated circuit structure, then exposing the integrated circuit structure to an elevated temperature. Then a second thin layer of dielectric material is deposited immediately overtop of the first thin layer of dielectric material, and then the integrated circuit structure is again exposed to an elevated temperature. The process is carried out to insure that the composite layer comprising the first and second deposited thin dielectric layers, after heat treatment, exhibits a residual stress which is compressive. The steps of depositing an additional thin dielectric layer and then exposing the semiconductor wafer to an elevated temperature may be repeated until a sufficient composite thickness of dielectric material has been formed, typically about 5000 Å to about 10,000 Å.