logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6230293 B1

PDFFull Text
Date of Patent:
May. 08, 2001

Filed:

Jul. 24, 1998

Method for quality and reliability assurance testing of integrated circuits using differential iddq screening in lieu of burn-in

Applicant:
Inventors:

Sailesh Chittipeddi, Allentown, PA (US);

Daryl E. Diehl, Bethlehem, PA (US);

Thomas N. Hofacker, Northampton, PA (US);

Richard J. Jenkins, Allentown, PA (US);

Mamata Patnaik, Windmere, FL (US);

Robert T. Smith, Coopersburg, PA (US);

Michael J. Toth, New Ringgold, PA (US);

Keelathur N. Vasudevan, Macungie, PA (US);

Michael Washko, Barto, PA (US);

Assignee:

Lucent Technologies Inc., Murray Hill, NJ (US);

Attorney:
Primary Examiner:

Phung M Chung

Int. Cl.
CPC ...
G01R 3/128 ;
U.S. Cl.
CPC ...
G01R 3/128 ;
Abstract

A method for quality and reliability assurance testing a lot of fabricated ICs comprising the steps of testing the differential I,of a sample of ICs at a plurality of different voltages, burning-in a sample of ICs, and then testing the functionality of the sample of ICs. The method of the present invention enables the reliability of an entire lot of ICs to be tested by determining an effective screening voltage for differential I,testing of the ICs, thereby eliminating the need both to burn-in and conduct post burn-in testing of all future lots of the ICs. The method of the present invention also enables fabrication facilities and workers to be engaged in other tasks rather than testing of ICs.

Find Patent Forward Citations

Chittipeddi, Sailesh. (2001). Method for quality and reliability assurance testing of integrated circuits using differential iddq screening in lieu of burn-in (U.S. Patent No. 6230293). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6230293

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…