Semiconductor memory device capable of preventing mis-operation due to load of column address line

Abstract

A semiconductor memory device is provided that is capable of operating normally and having its operating speed unaffected, even when column address lines for transmitting column addresses are greatly loaded and even when the loads on the column address lines are simultaneously different from one another. The semiconductor memory device includes a column selection line driver for receiving decoded addresses and driving column selection lines of a memory cell array in response to a column selection line control signal, a column selection line control signal generator for receiving buffered column address data, and for generating the column selection line control signal in response to an internal clock signal and one of a first control signal and a second control signal, and a control signal generator for generating the first and second control signals in response to the internal clock signal, an externally-input column address strobe signal, and an externally-input write enable signal.