The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2001

Filed:

Dec. 14, 1999
Applicant:
Inventor:

Shu-Chuan Lee, Changhua, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/362 ; H01L 2/974 ; H01L 3/1111 ;
U.S. Cl.
CPC ...
H01L 2/362 ; H01L 2/974 ; H01L 3/1111 ;
Abstract

The present invention discloses an ESD damage immunity buffer, comprising: a gate, a first doped region, a second doped region, a third doped region, and a resist layer. The ESD damage immunity buffer, which is in parallel with an ESD protection circuit, is connected to a pad and the circuit grounding node. The gate is formed on the semiconductor substrate, and the first doped region and the second doped region are formed adjacent to the region below the gate in the semiconductor substrate and electrically coupled to the ground. The third doped region is formed in the semiconductor substrate and electrically coupled to the pad. Further, a resist layer is formed upon the semiconductor substrate and connects the third doped region to the second doped region, wherein said resist layer ensures a triggering of the ESD protection circuit prior to the ESD damage immunity buffer during an ESD event.


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