The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2001
Filed:
Mar. 21, 2000
Yelehanka Ramachandramurthy Pradeep, Singapore, SG;
Vijai Kumar Chhagan, Belgrave, GB;
Henry Gerung, Singapore, SG;
Madhusudan Mukhopadhyay, Singapore, SG;
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
Abstract
A new method of forming metal interconnects with air gaps between adjacent interconnects in the manufacture of an integrated circuit device is achieved. A semiconductor substrate is provided. The metal interconnects are formed overlying the semiconductor substrate. A silicon nitride liner layer is deposited. A gap filling oxide layer is deposited to fill gaps between adjacent metal interconnects. The gap filling oxide layer is polished down to the silicon nitride liner layer. A silicon nitride thin layer is deposited. The silicon nitride thin layer is patterned using an oversized, reverse mask of the metal interconnects. The patterning of the silicon nitride thin layer creates openings to thereby expose a portion of the gap filling oxide. The gap filling oxide layer is etched away. A self-sealing oxide layer is deposited overlying the silicon nitride thin layer and the silicon nitride liner layer. The self-sealing oxide layer seals over the gaps between the silicon nitride thin layer and the silicon nitride liner layer to thereby form permanent air gaps between the adjacent metal interconnects, and the integrated circuit is completed.