Method for manufacturing dynamic random access memory

Abstract

A method for manufacturing dynamic random access (DRAM) memory. A substrate has a plurality of active regions marked out by shallow trench isolation (STI) structures therein. A conductive layer and a barrier layer are formed over the substrate. The conductive layer and the barrier layer are patterned to form bit line contact openings and node contact openings so that a portion of the active region and the shallow trenches are exposed. In the meantime, a word line inside the active region is also patterned out. Source/drain terminals are formed in the active regions. A bit line plug is formed inside each bit line contact opening, and a landing pad is formed inside each node contact opening. An oxide layer is formed over the bit line plugs and the landing pads. A word line patterning operation is conducted to establish the word line structures. A first dielectric layer is formed over the substrate, and then a bit line structure that connects with the bit line plug is formed in the first dielectric layer. A second dielectric layer is formed over the first dielectric layer, and finally a capacitor that connects electrically with a landing pad is formed above the second dielectric layer.