The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2001

Filed:

Jul. 23, 1999
Applicant:
Inventors:

Richard C. Ruby, Menlo Park, CA (US);

Tracy E. Bell, Campbell, CA (US);

Frank S. Geefay, Cupertino, CA (US);

Yogesh M. Desai, San Jose, CA (US);

Assignee:

Agilent Technologies, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

A microcap wafer-level package is provided in which a micro device is connected to bonding pads on a base wafer. A peripheral pad on the base wafer encompasses the bonding pads and the micro device. A cap wafer is processed to form wells of a predetermined depth in the cap wafer. A conductive material is made integral with the walls of the wells in the cap wafer. The cap wafer has contacts and a peripheral gasket formed thereon where the contacts are capable of being aligned with the bonding pads on the base wafer, and the gasket matches the peripheral pad on the base wafer. The cap wafer is then placed over the base wafer so as to bond the contact and gasket to the pads and form a hermetically sealed volume within the peripheral gasket. The cap wafer is thinned to form a “microcap”. The microcap is thinned below the predetermined depth until the semiconductor dopant is exposed to become conductive vias through the cap wafer to outside the hermetically sealed volume.


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