The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2001
Filed:
Jun. 28, 1999
Naoyoshi Watanabe, Tokyo, JP;
Advantest Corporation, Tokyo, JP;
Abstract
A timing signal generating apparatus capable of automatically detecting any erroneous set state that a pulse duration of a test pattern signal and a time duration between adjacent two pulses of the test pattern signal have been set in a program with the durations being shorter than corresponding limit values respectively, and a method of detecting any set error to the program for a timing signal. At the outside of a clock generator,A for generating a set pulse P,and a reset pulse P,are provided a fourth latch circuit,for latching therein an integer delay signal MT outputted from a down-counter,of an integer delay giving device,, and a fifth latch circuit,for latching therein an odd value MDAT outputted from a first latch circuit,of the integer delay giving device,, thereby to detect a time duration from the set pulse until the reset pulse or a time duration from the reset pulse until the set pulse. If the time duration is shorter than a limit value WMT,or WMT,, a logical signal indicating a set error is generated.