Fully recessed semiconductor method for low power applications with single wrap around buried drain region

Abstract

A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate. In one embodiment of the present invention the buried drain region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a drain junction disposed along portions of the sidewall and bottom of the trench, and the buried source region has a lower boundary which is approximately less than the depth of the trench. In another embodiment of the present invention the buried source region has a lower boundary which partially extends laterally underneath the bottom surface of the trench to form a source junction disposed along portions of the sidewall and bottom of the trench, and the buried drain region has a lower boundary which is approximately less than the depth of the trench. In one embodiment of the present invention, sidewall dopings are formed in the substrate to shield the trenched control gate from the buried source and buried drain regions.