Receiver employing digital filtering for use with an implantable medical device

Abstract

A receiving and filtering circuit includes an antenna, a demodulator circuit coupled to the antenna, and a digital median filter that removes high frequency content of a demodulated digital information signal to produce a filtered digital information signal corresponding to an analog data signal transmitted by a body implantable medical apparatus. The digital filter may include a multiple stage delay line coupled to a multiple tap selection device, a plurality of delay blocks coupled to a register, or a multiple stage delay line coupled to a voting unit. The voting unit produces a first binary output in response to a majority of delay line stages storing a first value, and produces a second binary output in response to a majority of delay line stages storing a second value. The digital filter may also comprise a digital signal processor. The digital filter may include a first filter block and a second filter block. The second filter block may be selectively activated or bypassed. The first filter block removes high frequency content of the digital information signal and the second filter block reduces high frequency noise at an edge of a data bit transition. A control circuit, coupled to the digital filter, provides for respective selection of data rate and frequency response characteristics of the digital filter. The digital filter may be implemented in a Field-Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).