Method and apparatus for managing access to a computer system memory shared by a graphics controller and a memory controller

Abstract

The shared computer system memory is partitioned between system memory and frame buffer memory. The frame buffer is configured as the top-most portion of the shared memory. A virtual memory manager controls access to the system portion of the shared memory. A virtual frame buffer device controls access to the frame buffer portion of the shared memory. While a frame buffer is defined, graphics operations, such as commands data, generated by a host CPU are routed to the memory manager by the virtual frame buffer device driver. Other graphics operations, such as those provided by peripheral devices interconnected via a PCI bus, are executed by the graphics controller. If an input buffer of the memory controller is full, graphics operations issued by the host CPU are rerouted onto the PCI bus for execution by the graphics controller. If no frame buffer is defined, then all graphics operations generated by the host CPU as well as all other PCI bus masters are transmitted over the PCI bus and are executed by the graphics controller. While a frame buffer is defined, memory access protocols and cache coherency protocols, described herein, are employed to prevent corruption of the data within the frame buffer portion of the shared memory. In one embodiment, the memory controller and the graphics controller both access the shared memory through a single interface bus. In an alternative embodiment also described herein, the shared memory is physically divided into two portions. The memory controller is interconnected by a first interface bus to both portions of the shared memory. The graphics controller is connected to only the second portion of the memory which is configured to include a frame buffer. As such, the memory controller may access system memory contained within the first portion of the shared memory while the graphics controller is accessing the frame buffer. In another alternative embodiment described herein, no graphics controller is provided. Rather, all graphics operations are performed directly by the host CPU. A frame buffer refresh unit takes the place of the graphics controller.