High selectivity mask oxide etching to suppress silicon pits

Abstract

A method for fabricating polycide gate electrodes wherein silicon pits in the active region are avoided by using a two-step etch to prevent pinholes in a BARC layer from penetrating significantly the silicide layer is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. A hard mask layer is deposited overlying the silicide layer. An anti-reflective coating layer is formed overlying the hard mask layer. A photoresist mask is formed over the anti-reflective coating layer wherein a pinhole is formed in the surface of the anti-reflective coating layer not covered by the photoresist mask. First the anti-reflective coating layer is etched through using O,and N,gases where it is not covered by the photoresist mask to the hard mask layer. Secondly, the hard mask layer is etched through using CHF,, CF,, Ar, and N,gases where it is not covered by the photoresist mask to the silicide layer wherein the pinhole in the anti-reflective coating layer does not significantly penetrate the silicide layer. The silicide, polysilicon and gate silicon oxide layers are patterned where they are not covered by the hard mask wherein since the pinhole does not significantly penetrate the silicide layer, formation of silicon pits in the semiconductor substrate is prevented.