The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2001
Filed:
Oct. 29, 1999
Mihai Manolescu, San Jose, CA (US);
Gianpaolo Spadini, Mesa, AZ (US);
Zilog, Inc., Campbell, CA (US);
Abstract
A method and circuits, in a non-volatile memory system such as EPROM, for limiting bit line current during programming that includes biasing a driving transistor to mirror a maximum desired current into the driving transistor from a mirroring transistor connected to a controlled current source. This technique is useful, for example, during hot electron programming of a floating gate memory cell to limit bit line current caused by snap back of the cell through which a relatively high current is passed. In a preferred embodiment, the state of a cell is monitored while being programmed by comparing the voltage of the bit line with a reference voltage that is developed in a circuit containing a replica of the driving transistor. Since characteristics of the driving and reference transistors are the same from wafer to wafer, or batch to batch, the reference voltage varies to compensate for variations in characteristics of the driving transistor among integrated circuit chips from different wafers and manufacturing batches.