The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2001
Filed:
Jan. 27, 1999
Suresh Manohar Menon, Sunnyvale, CA (US);
Yogendra Kumar Bobra, San Jose, CA (US);
Atul V. Ghia, San Jose, CA (US);
Arch Zaliznyak, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A programmable input/output structure comprised of three input circuits and one output circuit coupled to the pin of an FPGA with the input circuits and output circuits being selectively enabled by programming bits so that input signals may be accepted from TTL, GTL, GTLP, LVPECL or LVDS type external circuits. The programming bits can also selectively enable an output driver to simultaneously drive the same pin of the FPGA as an output with signals which are either TTL or GTL or GTLP compatible. Further, the slew rate of the output driver is programmable between slow, medium or fast.