The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2001

Filed:

Sep. 27, 1999
Applicant:
Inventors:

Jing-Xian Huang, Hsinchu, TW;

Jacson Liu, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ; H01L 2/18238 ; H01L 2/18234 ; H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/13205 ; H01L 2/14763 ; H01L 2/18238 ; H01L 2/18234 ; H01L 2/1336 ;
Abstract

A process for forming a contact structure of a semiconductor device includes the steps of (a) providing a substrate having a plurality of gates thereon and a first oxide layer formed between the gates, (b) forming a first dielectric layer on the oxide layer and the gates, (c) forming a second oxide layer on the first dielectric layer, and (d) removing a portion of the second oxide layer for forming first spacers alongside each of the gates. The process further includes steps of (e) removing a portion of the first dielectric layer and the first oxide layer to expose a portion of the substrate by using the first spacers as a mask for forming second spacers alongside each of the gates, (f) forming a second dielectric layer over the exposed portion of the substrate, the second spacers, and the gates, (g) forming a third dielectric layer over the second dielectric layer, and (h) executing a photolithographic and etching process on the third dielectric layer and the second dielectric layer to form the contact structure between the gates on the substrate.


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