The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2001
Filed:
Nov. 11, 1998
Jacson Liu, Hsin-Chu Hsien, TW;
Mosel Vitelic Inc., Hsin-chu, TW;
Abstract
The present invention relates to a shallow trench isolation method of a semiconductor wafer for filling dielectric material in each shallow trench between components on the surface of the semiconductor wafer to isolate the components electrically and prevent dishing when the chemical-mechanical polishing is performed on the surface of dielectric material in each shallow trench. The method comprises: (1) covering the surface of the semiconductor wafer with the dielectric material to form a first dielectric layer, filling the dielectric material in each shallow trench on the surface of the semiconductor wafer and the corresponding dish being formed above each shallow trench; (2) forming the second dielectric layer in each dish of the first dielectric layer; (3) polishing the surface of the semiconductor wafer to strip off the second dielectric layer in each dish of the first dielectric layer and cutting the surface of dielectric material in each shallow trench and on each component on the surface of the semiconductor wafer.