The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2001

Filed:

Jan. 28, 1999
Applicant:
Inventors:

Laertis Economikos, Wappingers Falls, NY (US);

Hussein Ibrahim Hanafi, Basking Ridge, NJ (US);

Thomas Safron Kanarsky, Hopewell Junction, NY (US);

Cheruvu Suryanarayana Murthy, Hopewell Junction, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18242 ;
U.S. Cl.
CPC ...
H01L 2/18242 ;
Abstract

A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.


Find Patent Forward Citations

Economikos, Laertis. (2001). Method of forming a buried bitline in a vertical dram device (U.S. Patent No. 6218236). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6218236

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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