The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2001

Filed:

May. 06, 1998
Applicant:
Inventors:

Yasutomi Asai, Okazaki, JP;

Takashi Nagasaka, Anjo, JP;

Shinji Ota, Okazaki, JP;

Takashi Yamazaki, Kokubu, JP;

Shinya Terao, Aira-gun, JP;

Syoichi Nakagawa, Kokubu, JP;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B32B 3/00 ; H01L 2/3485 ;
U.S. Cl.
CPC ...
B32B 3/00 ; H01L 2/3485 ;
Abstract

A multilayer circuit board for holding a flip chip thereon includes laminated first to fourth substrates. A first pattern integrated portion having a locally high pattern density is provided on the second substrate. Further, on the fourth substrate which is disposed on an opposite side of the second substrate with respect to a center in a laminated direction of the circuit board, a second pattern integrated portion having a locally high pattern density is disposed to correspond to the first pattern integrated portion. Accordingly, a local warp can be prevented from being produced on the mounting surface of the multilayer circuit board when the circuit board is manufactured by baking.


Find Patent Forward Citations

Asai, Yasutomi. (2001). Multilayer circuit board having no local warp on mounting surface thereof (U.S. Patent No. 6217990). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6217990

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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