Optimizing hardware and software co-verification system

Abstract

An optimizing hardware-software co-verification system is disclosed including a number of bus interface models, a number of memory models, and a co-verification optimization manager for co-verifying a hardware-software system having memory. Co-verification is performed with a single coherent view of the memory of the hardware-software system, transparently maintained by the co-verification optimization manager for both the hardware and software verifications. This single coherent view includes at least one segment of the memory being viewed as configured for having selected portions of the segment to be statically or dynamically configured/reconfigured for either unoptimized or optimized accesses, wherein unoptimized accesses are performed through hardware verification, and optimized accesses are performed “directly” by the co-verification optimization manager, by-passing hardware verification. Co-verification of a hardware-software system is performed with or without the co-verification optimization manager op mg verification time, which is statically or dynamically configured/reconfigured, and optionally in accordance to a desired clock cycle ratio between hardware and software verifications, also statically or dynamically configured/reconfigured.