Method and test structure for low-temperature integration of high dielectric constant gate dielectrics into self-aligned semiconductor devices

Abstract

A self-aligned semiconductor device including a high-K dielectric which is not exposed to elevated processing temperatures and a method for producing this device are provided. The method may also be used to fabricate a test structure, with which multiple combinations of gate dielectric/conductor configurations may be tested quickly and inexpensively. A self-aligned transistor is fabricated on a semiconductor substrate. Protective dielectrics are subsequently formed over the substrate and surrounding the transistor gate conductor such that upper surfaces of the dielectrics are even with the upper surface of the gate conductor. This dielectric-protected transistor forms a test structure which may be used to evaluate various gate dielectric/conductor configurations. The test structure is formed relatively simply using only two masking steps, and is believed to be particularly suited for evaluation of high-K gate dielectric configurations. The transistor gate conductor may be subsequently removed without disturbing the rest of the transistor. The removed gate conductor may be replaced with materials including high-K dielectrics, metals, and polysilicon. Because source and drain regions are formed before formation of the protective dielectrics, the gate dielectric/conductor materials used to replace the original gate conductor are not exposed to the elevated temperatures which may be used for impurity introduction.