The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2001
Filed:
May. 04, 1998
Applicant:
Inventors:
Henry Horng-Fei Jyu, Sunnyvale, CA (US);
An-Chang Deng, Saratoga, CA (US);
Assignee:
Synopsys, Inc., Mountain View, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A method for minimizing signal delay and power consumption is provided. Through combined power simulation and delay analysis, iterative transistor resizing is performed based on a variety of factors including relative delay of associated circuit paths, nodal switching activities and association of transistors in channel-connected sets.
Quick Actions:
Jyu, Henry Horng-Fei. (2001). Minimization of circuit delay and power through transistor sizing (U.S. Patent No. 6209122). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6209122
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile