The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2001

Filed:

Jul. 29, 1999
Applicant:
Inventors:

Glenn C. Abeln, Orlando, FL (US);

Robert Alan Ashton, Orlando, FL (US);

Samir Chaudhry, Orlando, FL (US);

Alan R. Massengale, Orlando, FL (US);

Jinghui Ning, Orlando, FL (US);

Assignee:

Lucent Technologies Inc., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18236 ;
U.S. Cl.
CPC ...
H01L 2/18236 ;
Abstract

A method for making an integrated circuit includes the steps of forming a plurality of spaced apart isolation regions in a substrate to define active regions therebetween, forming a first mask, and using the first mask for performing at least one implant in the active regions for defining high voltage active regions for the high voltage transistors. The method further includes the steps of removing the first mask and forming a second mask, and using the second mask for performing only one implant for converting at least one high voltage active region into a low voltage active region for a low voltage transistor. All of the implants needed to define the high voltage transistors are first performed throughout the active regions using the first mask. A separate single implant is then performed using the second mask to convert at least one of the high voltage active regions to a low voltage active region. A gate dielectric layer is formed on the high and low voltage active regions for corresponding high and low voltage transistors, and gates are formed on the gate dielectric layers.


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