The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2001

Filed:

Mar. 31, 1997
Applicant:
Inventors:

Paul William Coteus, Yorktown Heights, NY (US);

Robert Dominick Mirabella, Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/340 ;
U.S. Cl.
CPC ...
G06F 1/340 ;
Abstract

Memory cards for a computer system are placed back-to-back on an active backplane, using wiring topology where the memory address and data busses are wired to pairs of symmetrical connectors. This topology takes advantage of symmetrical memory card pinouts to improve memory bus performance while reducing backplane cost and wiring complexity. The symmetrical layout of the data and address wiring allows two memory cards to be placed back-to-back on the backplane, maintaining the same relative position of data and address pins between cards. Since the data and most of the address lines are common to each card, and any such data or (common or non-unique) address pin on one card can be wired to any other such data or address pin, respectively, on the other card, the back-to-back arrangement provides for minimal address and data bus interconnect lengths between connectors. Each data signal can be wired from a memory controller data pin on the first connector, then daisy-chained through the short printed circuit card wire to an adjacent pin on the second connector. Likewise, non-unique address pins can be connected from the memory controller to such address pins that are parallel between connectors. Those unique address and control signals which are to be connected together are placed as close as possible to the centerpoint of the edge connector.


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