Complementary heterostructure integrated single metal transistor fabrication method

Abstract

A method for fabricating a periodic table group III-IV metal semiconductor metal field-effect enhancement mode complementary transistor pair device is described, a device typically made of gallium arsenide materials. The disclosed fabrication uses initially undoped semiconductor materials, single metallization for ohmic and Schottky barrier contacts, employs a non-alloyed ohmic contact semiconductor layer and includes an inorganic dielectric material layer providing non photosensitive masking at plural points in the fabrication sequence. The invention uses selective ion implantations, and a combined optical and electron beam lithographic process, the latter in small dimension gate areas. These attributes are combined to provide a field-effect transistor complementary pair of reduced fabrication cost, low electrical energy operating requirements increased dimensional accuracy and current state of the art electrical performance. Fabricated device characteristics are also disclosed.