The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 2001
Filed:
Nov. 23, 1998
Mark I. Gardner, Cedar Creek, TX (US);
Mark C. Gilmer, Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A semiconductor process in which a low temperature oxidation of a semiconductor substrate upper surface followed by an in situ deposition of polysilicon are used to create a thin oxide MOS structure. Preliminarily, the upper surface of a semiconductor substrate is cleaned, preferably with a standard RCA clean procedure. A gate dielectric layer is then formed on the upper surface of the substrate. A first polysilicon layer is then in situ deposited on the gate dielectric layer. An upper portion of the first polysilicon layer is then oxidized and the oxidized portion is thereafter removed from the upper surface of the first polysilicon layer. A second polysilicon layer is subsequently deposited upon the first polysilicon layer. Preferably, the formation of the gate dielectric on the semiconductor substrate upper surface comprises annealing the semiconductor substrate in an ambient comprising an inert species and O,. The ambient temperature of the first oxidation chamber is preferably maintained at a temperature less than approximately 300° C. during the formation of the gate dielectric. The first polysilicon layer, in the preferred embodiment, is deposited in situ such that the semiconductor substrate remains within the first oxidation chamber during the deposition of the first polysilicon layer. The oxidation of an upper portion of the first polysilicon layer is preferably accomplished in a nitrogen bearing ambient so that nitrogen is introduced into the first polysilicon layer to inhibit the penetration of mobile impurities across the gate dielectric into the channel region of the transistor and enhance the device properties.