The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2001

Filed:

Aug. 31, 1999
Applicant:
Inventors:

King-Lung Wu, Tainan, TW;

Chuan-Fu Wang, Sun-Chung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1302 ; H01L 2/1461 ;
U.S. Cl.
CPC ...
H01L 2/1302 ; H01L 2/1461 ;
Abstract

A method of fabricating a narrow bit line structure is disclosed. The fabrication includes the steps as follows. At first, the interpoly dielectric layer is formed over the MOSFET. Then the landing pad is formed in the interpoly dielectric layer. Afterwards, the first polysilicon layer, the tungsten silicide layer, the silicon-oxy-nitride layer, and the second polysilicon layer is continuously formed over the interpoly dielectric layer. The defined photoresist layer is formed on the second polysilicon layer. A portion of the second polysilicon layer is etched, using the defined photoresist layer as a mask. Afterwards, the defined photoresist layer is removed. The polysilicon spacer is formed in the second polysilicon layer sidewall. The silicon oxide layer is deposited over the second polysilicon layer. Next, the silicon oxide layer is etched back to expose the second polysilicon layer. The second polysilicon layer, the polysilicon spacer, a portion of the silicon-oxy-nitride layer, a portion of the tungsten silicide layer, and a portion of the first polysilicon layer is Sequentially etched to expose the interpoly dielectric layer, using the silicon oxide layer as a hard mask. Afterwards, the silicon oxide layer is removed on the silicon-oxy-nitride layer. Finally, the narrow bit line structure is formed over the landing pad.


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