The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2001
Filed:
Jul. 29, 1999
David P. Schultz, San Jose, CA (US);
Lawrence C. Hung, San Jose, CA (US);
F. Erich Goetting, Cupertino, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A programmable logic device (PLD), such as a field-programmable gate array (FPGA), includes an integrated delay-locked loop that produces a lock signal internal to the FPGA. The FPGA also includes a sequencer and related global signals adapted to configure the FPGA using external configuration data. The sequencer disables the FPGA during the configuration process. The sequencer then continues to disable the fully configured FPGA until receipt of the lock signal. The configuration process, including the establishment of a valid internal clock, is controlled entirely within the FPGA. In one embodiment, an FPGA can be fully or partially reconfigured without powering down the device. The delay-locked loop maintains a lock on the clock signal so that the sequencer need not wait for the lock signal after reconfiguration.