The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2001

Filed:

Feb. 04, 1997
Applicant:
Inventors:

Don A. Tiffin, Austin, TX (US);

William S. Brennan, Austin, TX (US);

David Soza, Smithville, TX (US);

Patrick L. Smith, Austin, TX (US);

Allen White, Austin, TX (US);

Tim Z. Hossain, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/144 ;
U.S. Cl.
CPC ...
H01L 2/144 ;
Abstract

It has been observed that Si introduced into an Al metal line of an Al, Ti, and Si-containing layer stack of an integrated circuit, at concentrations uniformly less than the solid solubility of Si in Al, results in a reduction in Al metal line voiding. Such voiding is a stress induced phenomenon and the introduction of Si appears to reduce stresses in the Al metal lines. By controlling Ti deposition conditions to achieve desired thickness and grain-size characteristics of the Ti underlayer, a self-regulating filter for introduction of Si into the Al metal layer is provided. Si is introduced into the Al metal layer by migration through a suitably deposited Ti layer, rather than during Al layer deposition. In this way Si is introduced into the Al and Al metal line voiding is reduced, while avoiding excess concentration of Si which can result in formation of Si precipitates in the Al metal lines, thereby avoiding related reductions metal line cross-sections and reducing electromigration-induced open circuit failures.


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