The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2001
Filed:
Jan. 19, 2000
Ping-wei Lin, Chia Yi, TW;
Chien-hung Chen, Yung Ho, TW;
Jui-ping Li, Yi Lan County, TW;
Yen-jung Chang, Yung Ho, TW;
Mosel Vitelic Inc., Hsinchu, TW;
Abstract
A method for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps. First, a polycrystalline silicon layer with an enough thickness is deposited on the surface of the semiconductor substrate to overfill the trench. At least one dimple is undesirably developed on the polycrystalline silicon layer during the polycrystalline silicon deposition. Then, an oxide layer with an enough thickness is formed on the polycrystalline silicon layer to overfill the at least one dimple. Next, the polycrystalline silicon layer is partially oxidized so as to transform the upper portion thereof into a polysilicon oxide layer. As a result of a non-uniform distribution of the oxidization rate, the bottom surface of the polysilicon oxide layer, i.e. the interface between the polysilicon oxide layer and the non-oxidized portion of the polycrystalline silicon layer, is substantially planar. Finally, the oxide layer and the polysilicon oxide layer are both removed so as to expose the substantially planar polycrystalline silicon layer.