The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2001

Filed:

Nov. 24, 1998
Applicant:
Inventors:

Seiichi Shishiguchi, Tokyo, JP;

Tomoko Yasunaga, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A fabrication method of a semiconductor device with an IGFET is provided, which makes it possible to decrease the current leakage due to electrical short-circuit between a gate electrode and source/drain regions of the IGFET through conductive grains deposited on its dielectric sidewalls. After the basic structure of the IGFET is formed, first and second single-crystal Si epitaxial layers are respectively formed on the first and second source/drain regions by a selective epitaxial growth process. Then, the surface areas of the first and second single-crystal Si epitaxial layers are oxidized, and the oxidized surface areas of the first and second single-crystal Si epitaxial layers are removed by etching. If unwanted grains of poly-Si or amorphous Si are grown on the first and second dielectric sidewalls in the selective epitaxial growth process, the unwanted grains are oxidized and removed, thereby preventing electrical short-circuit from occurring between the gate electrode and the first and second source/drain regions through the unwanted grains deposited on the first and second dielectric sidewalls.


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