The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2001
Filed:
Oct. 07, 1998
Applicant:
Inventors:
Jiong Ping Lu, Dallas, TX (US);
Ming Hwang, Dallas, TX (US);
Dirk N. Anderson, Plano, TX (US);
Jorge A. Kittl, Plano, TX (US);
Hun-Lian Tsai, Dallas, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/13205 ;
U.S. Cl.
CPC ...
H01L 2/13205 ;
Abstract
A process for forming a W-poly gate stack (,) comprising the steps of: (1) deposition of doped polysilicon (,) on a thin dielectric layer (,) covered substrate (,), (2) deposition of WNx by a CVD-based process, (3) thermal treatment to covert WNx into thermally stable barrier, WSiNx, (,) and to remove excess nitrogen and (4) deposition of W layer (,). The stack layers are then etched to form the gate electrode (,).