Method for increasing isolation ability using shallow trench

Abstract

A method for increasing isolation ability is disclosed. A shallow trench into semiconductor device is formed on a wafer. Therefore the wafer owns a semiconductor substrate and wherein a first gate oxide layer is formed on the semiconductor substrate. A nitride layer is formed on the gate oxide layer. Then the method will include the following statement. Firstly a deep well layer is formed into the semiconductor substrate. Then patterning oxide layer and the nitride layer is carried out. Thereafter trenches is formed. The portion of silicon nitride layer and gate oxide layer will be etched according to the pattern of the gate oxide layer and the nitride layer. Sequentially first implanting a couple of device cell into the deep well of semiconductor substrate is achieved. Then the couple of device cell is annealed. The whole silicon nitride layer is removed. Not only the second implanting cell device will be obtained but also the third implanting cell device will be achieved. The first gate oxide layer is removed. A second gate oxide, a polysilicon layer and a tungsten silicide layer are in sequence deposited. Then the polysilicon gate is defined. The polysilicon gate is etched that abuts between the couple of cell device. Cell isolation implanted behind the trench wherein the isolation is formed thus excited between said couple of cell device. The cell device and cell isolation both are annealed. Consequentially a silicon oxide is conformably deposited in order to fulfill the trench. Finally the surface of silicon oxide is planarized.