The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2001
Filed:
Dec. 10, 1999
Wei-Ray Lin, Taipei, TW;
Hsien-Wen Liu, Taoyuan Hsien, TW;
Nanya Technology Corporation, , TW;
Abstract
A method of fabricating a crown capacitor comprises first providing a substrate having a transistor, constituted by at least one diffused region, formed thereon and overlaid by a first insulating layer. Bit lines are formed in the first insulating layer. A first masking layer and a second insulating layer are sequentially formed over the substrate. The second insulating layer, the first masking layer and the first insulating layer are patterned to form a contact hole that exposes the diffused region. A second masking layer is conformally formed and etched back to form masking spacers on the sidewalls of the contact hole. The second insulating layer is removed. A first conductive layer is conformally formed over the first masking layer and extending to the surface of the masking spacers and the bottom of the contact hole. A third insulating layer is formed over the first conductive layer and fills the contact hole. The third insulating layer and the first conductive layer are patterned to the first masking layer leaving portions of the third insulating layer with vertical sidewalls over the contact hole. A second conductive layer is conformally formed and etched back to form conductive spacers on the sidewalls of the third insulating layer. The third insulating layer is removed to expose the conductive spacers and the first conductive layer as a bottom electrode. A capacitor dielectric layer and a top electrode are sequentially formed on the bottom electrode.