Method of fabricating a capacitor under bit line dram structure using contact hole liners

Abstract

A process for fabricating a DRAM capacitor structure, in which the capacitor upper plate structure is defined during the formation of bit line contact hole opening, and substrate contact hole opening procedure, eliminating the need for a specific upper plate, photolithographic masking procedure, has been developed. The process features isolating a polysilicon upper plate structure, during an isotropic RIE cycle, also creating an undercut polysilicon region, in the contact holes, which are opened simultaneously during the upper plate definition. Subsequent silicon nitride spacers, on the sides of the contact holes, provides insulation between the polysilicon upper plate structure, and bit line, and substrate contact plug structures, now located in the contact holes. The undercut polysilicon regions, allow the formation of thicker silicon nitride spacers, to be formed in this undercut region.