Passivation layer etching process for memory arrays with fusible links

Abstract

A method is described for progressively forming a fuse access openings in integrated circuits which are built with redundancy and use laser trimming to remove and insert circuit sections. The fuses are formed in a polysilicon layer and covered by one or more relatively thin insulative layers. An etch stop is patterned over the fuse in a higher level polysilicon layer or a first metallization layer. Additional insulative layers such as inter-metal dielectric layers are then formed over the etch stop. A first portion of the laser access window is then etched during the via etch for the top metallization level. The etch stop prevents removal of the insulation subjacent to it. Cumulative thickness non-uniformities in the relatively thick upper insulative layers are thus removed from the fuse window. The etch stop is removed during patterning of the top level metallization. A passivation layer is applied and patterned to exposed bonding pads and, at the same time complete the etching of the laser access window to a desired thickness over the fuses. The passivation layer over etch required to penetrate the insulation layer over the fuses also removes an ARC over the bonding pads. The process fit conveniently within the framework of an existing process and does not introduce any additional steps. In addition, the passivation layer can be patterned to form final access to both bonding pads and laser access openings with a single photolithographic mask.