Method of making high performance mosfet with channel scaling mask feature

Abstract

A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A dielectric layer is then formed on the surface of the substrate, portions of which are then etched to define a channel opening for the device. A uniform nitride layer is formed over the surface of the substrate. The nitride layer is then etched to create nitride sidewall spacers. Additionally, the channel region is then etched to remove the doped portions of the active region. A gate dielectric is then formed, the gate dielectric including a nitrogen bearing oxide and a high K material. A gate conductor is then formed upon the high K material. A silicidation step is then performed. In alternative embodiments, the source/drain region is not formed and the source and drain are doped after the gate is complete. In the embodiment, the gate resides upon the active region and etching into the active region is not required. In either case, with the channel opening created to be at a lower lithographic limit, the gate conductor has a width less than the lower lithographic limit.