Memory and system configuration for programming a redundancy address in an electric system

Abstract

A redundancy address in a plurality of memory devices is identified by at least two protocols available in an electric system. The first protocol is a mode register set command (or extended mode register set command). A chip select signal determines one of a plurality of memory modules, where a memory device is identified with at least one data port. Alternatively, a data strobe port or a data mask port may be preferably used for the selection of the memory devices instead of using the data port. The second protocol is a RAM access command which identifies a defective memory cell address (redundancy address) within the selected RAM by way of a plurality of address ports (ADRs). A redundancy address programming method is realized by way of electrically programmable fuses or by dynamically programmable redundancy latches integrated in each memory. The electric system configuration preferably includes a non-volatile storage device for storing a data port organization for the memory devices. Therein, the relation between the system memory data bus and the memory data ports for the memory devices are recognized by a memory controller. A microprocessor in the electric system is used for testing the memories and for analyzing the redundancy address. The present invention further includes a post device identification protocol to effectively debug field problems.