Source/drain and lightly doped drain formation at post interlevel dielectric isolation with high-k gate electrode design

Abstract

An integrated circuit fabrication process is provided in which a gate electrode including a gate dielectric and a gate conductor is formed upon a semiconductor substrate. Preferably, the gate dielectric has a dielectric constant greater than the dielectric constant of silicon dioxide. In an embodiment, sidewall spacers are formed laterally adjacent opposed sidewall surfaces of the gate electrode. An interlevel dielectric is then formed above the semiconductor substrate and selectively removed from above active regions of the semiconductor substrate to form an opening. Source and drain implant areas are formed self-aligned with the opposed sidewall spacers. A metal silicide layer may be formed across upper surfaces of the gate conductor and source and drain areas, a second interlevel dielectric deposited in the opening, and contacts formed through the second interlevel dielectric to the metal silicide. In an alternative embodiment, the gate dielectric may be formed sufficiently thick such that sidewall spacers are unnecessary to prevent silicide bridging between the gate conductor and the junction regions. In another alternative embodiment, the lightly doped drain implant areas may be formed self-aligned to the gate electrode prior to spacer formation.