Semiconductor memory device using shared sense amplifier system

Abstract

In the present invention, the gate electrodes of the bit line transfer gates for bit line pair selection that perform connection and isolation of the sense amplifiers and bit line pairs are put into floating condition during activation of the sense amplifier in the active period. Thus, a system is adopted according to which the potential of the bit line is driven to power source voltage Vcc or high voltage corresponding thereto by the sense amplifier in the active condition, the pre-charging potential of the bit line pair being made lower than half the power source voltage Vcc, for example ground potential Vss. Thanks to the amplification action of the sense amplifier, by utilising the fact that one side of the plurality of bit line pairs is inevitably driven from low potential to the power source voltage Vcc level or high voltage corresponding thereto, the potential of the gate electrodes which are in floating condition is boosted higher due to capacitative coupling, enabling the potential of the bit line on rewriting to be boosted to a voltage driven by the sense amplifier, for example power source voltage.