Adjustable serial-to-parallel or parallel-to-serial converter

Abstract

A clock synchronizer may include two programmable counters, one which may be programmed with a bit-rate value so that it generates a signal approximately matching the bit rate of the asynchronous data signal, and the other programmed with a phase-delay value so that it generates a sample clock signal at a phase delay from the signal generated by the first counter. The phase of the sample clock may be adjusted by restarting the counters in response to a transition on the asynchronous data signal. Data may be supplied to a serial-to-parallel converter including a first shift register configured to shift a data word in serially and output the data word in parallel and a second shift register configured to track when the data word had been completely shifted into the first shift register and to cause the data word to be outputted in parallel from the first shift register so that a new word may be shifted into the first shift register. A status value may be loaded into the second shift register so that when the last bit is converted in the first shift register, the second shift register shifts out a conversion completed indication. The bit length to be converted may be changed by loading a different status value into the second shift register. This same technique may be employed in a parallel-to-serial data converter or in a general data converter that may convert from serial-to-parallel or parallel-to-serial according to a conversion-type signal.