The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2001
Filed:
Feb. 26, 1998
Yohei Ishikawa, Kyoto, JP;
Koichi Sakamoto, Nagaokakyo, JP;
Sadao Yamashita, Kyoto, JP;
Takehisa Kajikawa, Osaka, JP;
Abstract
A planar dielectric integrated circuit is provided such that energy conversion loss between a planar dielectric line and electronic components is small and that impedance matching between them can be easily obtained. By providing slots which oppose both main surfaces of a circuit substrate, two planar dielectric lines are constructed. A slot line, and a first line-conversion conductor pattern which is connected to the electromagnetic field of the slot line and a first planar dielectric line in order to perform line conversion, are provided at the end portion of the first planar dielectric line, including a slot. A coplanar line and a second line-conversion conductor which is made to project in a direction at right angles to a second planar dielectric line is provided at the end portion of the second planar dielectric line, including a slot. A semiconductor device is placed in such a manner as to be extended over the coplanar line and the slot line.