The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2001
Filed:
May. 26, 1999
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method for making crown capacitors using a new and improved crown etch window process for DRAM cells is described. After forming FETs for the memory cells, a planar first insulating layer (IPO-1) is formed and bit lines are formed thereon. A second insulating layer (IPO-2) is deposited, and a first etch-stop layer and a disposable insulating layer are deposited. Contact openings are etched in the layers to the substrate, and are filled with a polysilicon to form capacitor node contact plugs. The disposable layer is removed to expose the upper portions of the plugs extending above the first etch-stop layer. A second etch-stop layer is deposited and a thick insulating layer is deposited in which capacitor openings are etched over and to the plugs. The capacitor openings can be over-etched in the thick insulating layer because the plugs extend upward thereby allowing all the plugs to be exposed across the wafer without overetching the underlying IPO-2 layer that would otherwise cause capacitor-to-bit-line shorts when the bottom electrodes are formed in the capacitor openings.