Method for fabricating crown-shaped capacitor structures

Abstract

The memory cell, such as a DRAM, has a crown-shaped capacitor structure and is formed on a substrate having a first conductivity type (i.e., p-type) and preferably has the following structure. Portions of the substrate are doped to have a conductivity type opposite that of the substrate (i.e, n-type) to form drain and source regions. A gate is formed between the drain and source regions having a gate oxide adjacent the substrate, a first polysilicon region (Poly-1), tungsten silicide layer, and an oxide layer and Si,N,, respectively, on the gate oxide. Si,N,spacers cover the sides of the gate regions. Above the oxide layer are tetetraethylorthosilicate (TEOS) and borophosphosilicate (BPSG) layers. A second polysilicon layer (Poly-2) is patterned to form a bitline which contacts the source region. A layer of tungsten silicide, oxide, and Si,N,are formed on top of the bitline. Si,N,spacers surround the bitline. A crown-shaped capacitor contacts the drain region. The crown-shaped capacitor comprises two polysilicon electrodes (Poly-3, Poly-4) separated by a thin dielectric layer. The inventive method fabricates the DRAM cell using only five masking steps. Thus, the process is more efficient than the prior art method for fabricating other DRAMS having crown-shaped capacitors. Also, the drain is exposed at the same time that the grid is formed using Si,N,spacers for etch self-alignment. This avoids precise masking or photolithography to expose this layer.