System and method for testing interrupt processing logic within an

Abstract

A system and method is provided for selectively injecting interrupts within the instruction stream of a data processing system. The system includes a programmable storage device for storing interrupt injection signals, each of which is associated with a respective machine instruction. When execution of the associated machine instruction is initiated, the stored signal is read from the storage device and is made available to the interrupt logic within the instruction processor. If set to a predetermined logic level, the signal causes an interrupt to be injected within the instruction processor. The system provides the capability to simultaneously inject different types of interrupts, including fault and non-fault interrupts, during the execution of any instruction. The invention further provides a programmable means for injecting errors at predetermined intervals in the instruction stream. Because the current invention allows interrupt injection to be controlled by programmable logic within the instruction processor itself instead by stimulus generated and controlled by a simulation program as in prior art systems, there is no need to develop complex simulation programs to generate and control the external stimulus. Any simulation program can utilize the interrupt injection system to test the interrupt logic. Furthermore, the injected interrupts are handled in a manner which is transparent to the system software, which makes development of test-version interrupt handling code unnecessary. Moreover, the interrupt injection system may be used during normal (non-test) situations to place the instruction processor under microcode control. This can be useful to provide temporary fixes to hardware problems in a manner which is transparent to the operating system.