The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2000
Filed:
Mar. 25, 1998
Yoshinori Odake, Osaka, JP;
Matsushita Electronics Corporation, Osaka, JP;
Abstract
LOCOS layers for defining NMOSFET and PMOSFET forming regions Rn and Rp are formed, and then a protective oxide layer is formed. A first resist layer, opened above the region Rn, is then formed on the protective oxide layer. By using the first resist layer as a mask, ion implantation is performed twice to form a threshold control layer and a P- layer functioning as a punch-through stopper or the like. By using the first resist layer as a mask, the substrate is etched to remove a portion of the protective oxide layer. Then, the first resist layer is removed. These processes are also performed on the region Rp. Then, a gate oxide layer is formed. Thus, it is possible to prevent a foreign impurity, introduced during the ion implantation, from diffusing the surrounding regions when the resist layers are removed. As a result, the properties of the gate oxide layer can be improved.