The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2000

Filed:

Jan. 26, 1998
Applicant:
Inventors:

Cau L Nguyen, Fremont, CA (US);

Harini G Setlur, Cupertino, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
711119 ; 711120 ; 711143 ; 711144 ; 711145 ;
Abstract

An apparatus to identify a storage device of a processor within a digital system is described. The processor includes a first storage device designed to generate a first signal when the first storage device contains a copy of a requested entry in a main storage device. The first signal is in a first state when the copy is of a first type and is in a second state when the copy is of a second type. A second storage device is included that is designed to generate a second signal when the second storage device contains the copy of the requested entry in the main storage device. The second signal is in the first state when the copy is of the first type and is in the second state when the copy is of the second type. The processor also includes a first logic device that generates a first indicator signal in response to receiving the first signal, and is coupled to the first storage device. The indicator signals are representative of the storage device that contains. The processor is also designed such that the first indicator signal is applied to a first pin. A method for identifying a storage device in a processor includes generating a common signal on a bus in a digital system. A first indicator signal is generated in response to receiving a first signal from a first storage device. A second indicator signal is generated in response to receiving a second signal from a second storage device. The processor is identified as the originator of the common signal in response to analyzing the indicator signal and the common signal.


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